1. Field of the Invention
The present invention relates to sense amplifiers and, more particularly, to a sense amplifier that has a bias circuit with a reduced size.
2. Description of the Related Art
A dynamic random access memory (DRAM) cell is a memory device that retains data stored in the cell for only a short period of time even when power is continuously applied to the cell. As a result, a DRAM cell must be periodically refreshed to maintain the data stored in the cell.
FIG. 1 shows a cross-sectional diagram that illustrates a conventional DRAM cell 100. As shown in FIG. 1, DRAM cell 100 includes an access transistor 102 which is formed in a p-type material 110, and a capacitor 104 which is connected to transistor 102.
Access transistor 102, in turn, includes spaced-apart source and drain regions 112 and 114 which are formed in material 110, and a channel region 116 which is defined between regions 112 and 114. In addition, transistor 102 also includes an access gate 120 which is insulatively formed over channel region 116.
As further shown in FIG. 1, capacitor 104 includes a lower plate 124 which is connected to drain region 114, a dielectric layer 126 which is formed over lower plate 124, and an upper plate 128 which is formed over dielectric layer 126.
In operation, a logic "one" is written to DRAM cell 100 by first placing a programming voltage, such as five volts, on source region 112 while a storage voltage, such as five volts, is applied to the top plate 128 of capacitor 104 and ground is applied to material 110. The storage voltage (which is continuously applied to top plate 128) attracts electrons to the lower plate 124 of capacitor 104 where the electrons begin to accumulate.
After placing a programming voltage on source region 112, access gate 120 is pulsed with an access voltage. This pulse turns on access transistor 102 which causes the electrons on the lower plate 124 of capacitor 104 to flow to source region 112.
The electrons flow from the lower plate 124 of capacitor 104 to source region 112 because the lower plate 124 of capacitor 104 has a potential which is less than five volts (some of the applied voltage is dropped across dielectric layer 126), while source region 112 is at five volts.
When the trailing edge of the pulse again turns off access transistor 102, a positive potential is stored on the lower plate 124 of capacitor 104 due to the decreased number of electrons which are present on the lower plate 124 of capacitor 104.
This positive potential, however, lasts only a short time because electrons from leakage currents are readily attracted to the positive potential. As a result, the positive charge stored on the lower plate 124 of capacitor 104 must be "refreshed" by periodically removing the electrons from the lower plate 124 of capacitor 104.
DRAM cell 100 is erased (a logic "zero" is written to a DRAM cell which already has a logic "one" stored in the cell) by placing ground on source region 112. Once ground has been applied to source region 112, access gate 120 is again pulsed with the access voltage.
This pulse turns on access transistor 102 which causes the electrons in source region 112 to flow to the lower plate 124 of capacitor 104. The electrons flow from source region 112 to the lower plate 124 of capacitor 104 because the lower plate 124 of capacitor 104 has a greater potential than source region 112.
When the trailing edge of the pulse again turns off access transistor 102, the positive potential stored on the lower plate 124 of capacitor 104 is removed due to the increased number of electrons which are again present on the lower plate 124 of capacitor 104.
Due to the overhead required to refresh DRAM cells, large numbers of DRAM cells like cell 100 are typically grouped together to form a memory array. FIG. 2 shows a schematic diagram that illustrates a conventional DRAM array 200.
As shown in FIG. 2, DRAM array 200 includes a plurality of DRAM cells 100 which are formed in rows and columns in two segments S1 and S2. As further shown in FIG. 2, array 200 also includes a plurality of first bit lines BL1-BLm and a plurality of second bit lines BLC1-BLCm.
The first bit lines BL1-BLm are formed adjacent to the columns of cells in first segment S1 so that each bit line BL is connected to all of the source regions 112 in a column of cells. Similarly, the second bit lines BLC1-BLCm are formed adjacent to the columns of cells in second segment S2 so that each bit line BLC is connected to all of the source regions 112 in a column of cells.
Array 200 further includes a plurality of first word lines WL1-WLn and a plurality of second word lines WLC1-WLCn. The first word lines WL1-WLn are formed adjacent to the rows of cells in first segment S1 so that each word line WL is connected to all of the access gates 120 in a row of cells. Similarly, the second word lines WLC1-WLCn are formed adjacent to the rows of cells in second segment S2 so that each word line WLC is connected to all of the access gates 120 in a row of cells.
As additionally shown in FIG. 2, array 200 includes a sense circuit 210 which has a plurality of sense amplifiers SA1-SAm that are connected to the bit lines BL1-BLm and BLC1-BLCm so that each sense amplifier SA is connected to a bit line from each segment S1 and S2.
Each sense amplifier SA includes a first invertor which is formed from transistors M1 and M3, and a second invertor which is formed from transistors M2 and M4. In addition, each sense amplifier SA also includes a power switch transistor M5 and a ground switch transistor M6.
Each power switch transistor M5 provides power to a sense amplifier SA when a first turn on voltage is applied to a power switch line PSL, while each ground switch transistor M6 connects ground to a sense amplifier SA when a second turn on voltage is applied to a ground switch line GSL.
In operation, a cell is programmed by placing a programming voltage, such as five volts, on the bit line that corresponds with the cell to be programmed, while ground is applied to the remaining bit lines. (A storage voltage, such as five volts, is continuously applied to the top plate 128 of each capacitor 104 and ground is applied to material 110.)
After placing a programming voltage on the bit line, the word line that corresponds with the cell to be programmed is pulsed with an access voltage while ground is applied to the remainder of the word lines. This pulse turns on the access transistor 102 which causes the electrons on the lower plate 124 of capacitor 104 to flow to source region 112.
For example, if cell A in FIG. 2 is to be programmed, the programming voltage is applied to bit line BL1 while ground is applied to bit lines BL2-BLm and BLC1-BLCm. In addition, word line WL1 is pulsed with the access voltage while word lines WL2-WLn and WLC-WLCn are connected to ground.
To read a row of cells, ground is placed on the bit lines in the segment that contain the row of cells to be read, while a logic high voltage is placed on the bit lines in the remaining segment. (Since the sense amplifiers SA are based on cross-coupled inverters, the logic states on the bit lines in one segment are always the opposite of the logic states on the bit lines in the other segment.) Once the voltages have been placed on the bit lines, the bit lines are isolated so that the bit lines are only connected to the sense amplifiers SA.
After this, a read voltage, such as five volts, is applied to the word line that corresponds to the row of cells to be read, while ground is applied to the remainder of the word lines. If a cell in the row is storing a logic zero, nothing happens.
On the other hand, if a cell in the row is storing a logic one, the positive potential on the capacitor in the cell raises the voltage on the bit line which, in turn, causes the inverters in the sense amplifier to flip. The logic state stored by is the cell is then determined by reading the state of the inverters. Since the read step is similar to the step of erasing a programmed cell, each programmed cell must be refreshed after it is read.
For example, if the first row of cells in segment 2 is to be read, ground is placed on bit lines BLC1-BLCm, while a logic high voltage is placed on bit lines BL1-BLm. Once the bit lines have been isolated, the read voltage is applied to word line WLC1 while ground is applied to word lines WLC2-WLCn and WL1-WLn.
One problem with array 200 is that when ground is applied to a bit line during a read operation of the array, each programmed cell 100 in the same column of cells 100 that has access gate 120 connected to ground also has a small sub-threshold leakage current that flows from drain region 114 to source region 112 which, in turn, undesirably erases the cell.
One technique for reducing this sub-threshold leakage current is to place a small positive voltage, e.g., 0.1-0.3 volts, rather than ground on the bit lines that are to be read. One technique for providing this small positive voltage is to use sense amplifiers that are biased by the small positive voltage.
FIG. 3 shows a schematic diagram that illustrates a conventional sense circuit 300. As shown in FIG. 3, sense circuit 300 is similar to sense circuit 210 of FIG. 2 and, as a result, utilizes the same reference numerals to designate the structures which are common to both amplifiers.
As shown in FIG. 3, sense circuit 300 differs from sense circuit 210 in that sense circuit 300 includes a bias circuit 310. Bias circuit 310, in turn, includes a first current source GEN1, a transistor M7 which has a drain and gate connected to current source GEN1, and a resistor R1 which is connected to the source of transistor M7 and ground.
In addition, bias circuit 310 also includes a second current source GEN2, a transistor M8 which has a source, a drain connected to current source GEN2, and a gate connected to the gate of transistor M7; and a transistor M9 which has a source connected to ground, a drain connected to the source of transistor M8, and a gate connected to current source GEN2.
In operation, the output of generator GEN1 is set so that a small positive reference voltage is dropped across resistor R1 in response to a reference current IREF flowing through transistor M7 and resistor R1.
The reference voltage and the reference current IREF are mirrored so that a bias voltage VLB equal to the reference voltage is present at a summing node NS (the source of transistor M8 and the drain of transistor M9), and so that a bias current ILB equal to the reference current IREF flows through transistor M8.
Summing node NS sums the bias current ILB and a sense amp current IS. When each transistor MS and M6 is turned off, the sense amp current IS, which represents the total current flowing out of the sense amplifiers SA, is substantially zero. In this case, transistor M9 sinks substantially only the bias current ILB.
On the other hand, when each transistor MS and M6 is turned on, the sense amp current IS is large. In this case, the voltage on node B rises in response to the increased current flow from the sense amplifiers SA which, in turn, turns transistor M9 on harder to sink a larger current that includes both the bias current ILB and the large sense amp current IS.
Thus, by forming a bias voltage VLB at the summing node NS, the voltage on a bit line during a read operation is equal to the bias voltage VLB plus the voltage drops across transistors M6 and transistors M3 or M4, depending on which segment is read.
One problem with bias circuit 310, however, is that bias circuit 310 consumes a significant amount of area. Thus, there is a need for a sense amplifier which has a bias circuit that consumes less silicon real estate.